It is known in the MOS art that semiconductor wafer-to-wafer processing variations result in corresponding variations in the threshold voltages of MOS transistors, particularly depletion mode load transistors. These variations result in undesirable threshold voltage shifts from the proper value suitable for preserving the desired high incremental resistance and these load transistors in the circuit.
In a typical input stage of an MOS amplifier circuit, a depletion load transistor is connected in series with an input driver transistor device and a current-source. Unless the threshold voltage of the load transistor is controlled with a precision sufficient to provide during operation the correct amount of voltage drop for a given current-source, the biasing of the input driver device in series with this load transistor will not be suitable for achieving the desired high gain and linearity of the amplifier circuit. However, the correspondingly required precision of processing control is difficult, if at all possible, to achieve even in present day advanced processing technology. Moreover, variations in voltage supplies can also similarly deteriorate the gain of the amplifier.
In an application filed by Y. Tsividis (Ser. No. 010737) on Feb. 9, 1979, now U.S. Pat. No. 4,213,098 an amplifier circuit in MOS technology was described including a self-biased, stabilized differential amplifier stage that eliminated the need for precise matching of the threshold voltages of the depletion load transistors with the threshold voltages of the current-source transistors; that is, the circuit operation was relatively insensitive to processing variations. On the other hand, that circuit required a relatively large number of extra transistors; thereby the circuit achieved the purposes of that invention, but at the expense of a requirement of more silicon area.